1. Field of the Invention
The present invention relates to differential amplifier circuits, and in particular, to differential amplifier circuits implemented with complementary metal oxide semiconductor (CMOS) transistors in compact circuit structures which require no input signal terminal biasing while also providing substantially symmetrical dynamic input signal range.
2. Description of the Related Art
Referring to FIG. 1, conventional CMOS differential amplifiers typically use a stacked, or telescopic circuit structure in which multiple CMOS transistors are connected in series between the power supply terminals VDD, VSS/GND. The upper NMOS transistors M1, M2 are biased with a predetermined bias voltage Vbias to establish current flow and a nominal voltage potential for the terminal providing the output voltage Vout. The complementary PMOS transistors M3, M4 and NMOS transistors M5, M6 are biased at their drain terminals with a selected DC bias to establish the nominal center potential for the complementary phases Ip, Im of the differential input signal Ip-Im. A tail current transistor M7, biased by another bias voltage Vtail, establishes the tail current shared by the two circuit branches.
This conventional design has several disadvantages. One is that the input circuitry requires a DC bias to ensure that the differential input signal components are properly centered for maximum dynamic input signal range. Another is that the telescopic arrangement of the individual transistors causes the circuit to be more sensitive to temperature variations due to the resultant increased overall temperature coefficient. Additionally, particularly due to the various biasing potentials required, this circuit is very sensitive to variations in the power supply potential VDD-VSS/GND.